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quad, 15 v, 256 - position, digital potentiometer with pin - selectable spi/i 2 c data sheet ad5263 rev. f document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other r i ghts of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their res pective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2003 C 2012 analog devices, inc. all rights reserved. technical support www.analog.com features 256- position, 4 - channel end - to - end resistance 20 k?, 50 k?, 200 k? pin - selectable spi? - or i 2 c? - compatible interface power - on preset to midscale two package address decode pins ad0 and ad1 rheostat mode te mperature coefficient 30 ppm/c voltage di vider temperature coefficient 5 ppm/c wide operating temperature range C 40c to +125c 10 v to 15 v single supply; 5 v dual supply applications mechanical potentiometer replacement optical network adjustment instrumentati on: gain , offset adjustment ster eo channel audio level control automotive electronics adjustment programmable power supply programmable filters, delays, time constants line impedance matching low resolution dac/trimmer replacement base station power amp biasing sensor calibration functi onal block diagram 03142-001 serial input register ad5263 address decoder spi/i 2 c select logic gnd a1 w1 b1 a2 w2 b2 a3 w3 b3 a4 w4 b4 cs/ad0 sdi/sda clk/sc l v l v dd v ss shdn res/ad1 dis nc/o2 sdo/o1 rdac 1 register rdac 2 register rdac 3 register rdac 4 register 8 figure 1. general description the ad5263 is the industrys first quad - channel, 256 - position, digital potentiometer 1 with a selectable digital interface. this dev ice performs the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid - state reliability, and superior low temperature coefficient performance. each channel of the ad5263 offers a completely programmable value of resistance between the a terminal and the wiper or between the b terminal and the wiper. the fixed a - to - b terminal resistance of 20 k?, 50 k?, or 200 k? has a nominal temperature coeffic ient of 30 ppm/c and a 1% channel - to - channel matching tolerance. another key feature of this part is the ability to operate from +4.5 v to +15 v, or at 5 v. wiper position programming presets to midscale upon power - on. once powered, the vr wiper posi tion is programmed by either the 3 - wire spi or 2 - wire i 2 c- compatible interface. in the i 2 c mode, additional programmable logic outputs enable users to drive digital loads, logic gates, and analog switches in their systems. the ad5263 is available in a narrow body , 24 -lead tssop . all parts are guaranteed to operate over the automotive temperature range of C 40c to +125c. for single - or dual - channel applications, refer to the ad5260 / ad5280 or ad5262 / ad5282 data sheets . 1 the terms digital potentiometer , vr , and rdac are used intercha ngeably.
ad5263 data sheet rev. f | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 funct ional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 electrical characteristics 20 k?, 50 k?, 200 k? versions ....... 3 timing characteristics 20 k?, 50 k?, 200 k? versions .......... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and pin function descriptions ...................... 7 typical performance characteristics ............................................. 8 test circuits ..................................................................................... 13 spi - compatible digital interface (dis = 0) ................................ 15 serial data - word format .......................................................... 15 i 2 c- compatible digital interface (dis = 1) ................................ 16 i 2 c write m ode data - word format ........................................ 16 i 2 c read mode data - word format ......................................... 16 operation ......................................................................................... 17 programming the variable resistor ......................................... 17 programming the pot entiometer divider voltage output operation ..................................................................................... 18 pin - selectable digital interface ................................................ 18 spi - compatible 3 - wire serial bus (dis = 0) ......................... 18 i 2 c- compatible 2 - wire serial bus (dis = 1) .......................... 19 additional programmable logic output ................................ 20 self- contained shutdown function ........................................ 20 multiple devices on one bus ................................................... 21 level shift for negative voltage operation ................................ 21 esd protect ion ........................................................................... 21 terminal voltage operating range ......................................... 21 power - up sequence ................................................................... 21 v logic power supply ................................................................... 22 layout and power supply bypassing ....................................... 22 rdac circuit simulation model ............................................. 22 applications information .............................................................. 23 bipolar dc or ac operation from dual supplies ................. 23 gain co ntrol compensation .................................................... 23 programmable voltage reference ............................................ 23 8- bit bipolar dac ...................................................................... 24 bipolar programmable gain amplifier ................................... 24 programmable volt age source with boosted output ........... 24 programmable 4 to 20 ma current source ............................ 25 programmable bidirectional current source ......................... 25 programmable low - pass filter ................................................ 26 programmable oscillator .......................................................... 26 resistance scaling ...................................................................... 27 resistance tolerance, drift, and temperature coefficient mismatch considerations ......................................................... 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 10 /12 rev. e to rev. f change s to self- contained shutdown function section .......... 20 added table 8 and table 9; renumbered sequentially ............. 20 changes to programmable voltage source with boosted output section .............................................................................................. 24 7/12 rev. d to rev. e change s to sd description ........................................................... 16 4 /1 2 rev. c to rev. d change to rheostat operation section ....................................... 17 deleted equation 4 and accompanying text ............................. 18 5/11 rev. b to rev. c change to digital inputs and output voltage parameter .............. 6 changes to ordering guide .......................................................... 28 changes to i 2 c disclaimer ............................................................ 28 7 /0 9 rev. a to rev. b change to features section .............................................................. 1 change to power single - supply range parameter ........................ 4 changes to ordering guide .......................................................... 28 11/06 rev. 0 to rev. a updated format .................................................................. universal changes to absolute maximum ratings ........................................ 6 changes to ordering guide ................................ .......................... 28 6/03 revision 0: initial version
data sheet ad5263 rev. f | page 3 of 28 electrical character istics 20 k ?, 50 k ?, 200 k ? versions v dd = + 5 v, v ss = C 5 v, v l = +5 v, v a = +v dd , v b = 0 v, C 40c < t a < +125c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode specifications apply to all vrs resistor differential nl 2 r- dnl r wb , v a = nc ?1 1/4 +1 lsb resistor no nlinearity 2 r- inl r wb , v a = nc ?1 1/2 +1 lsb nominal resistor tolerance 3 ?r ab t a = 25c ? 30 + 30 % resistance mode temperature coefficient ?r wb /?t 30 ppm/c ?r wa /?t 30 ppm/c wiper resistance r w i w = 1 v/r ab 60 150 ? dc characteristics potentiometer divider mode specifications apply to all vrs resolution n 8 bits differential nonlinearity 4 dnl ?1 1/4 +1 lsb integral nonlinearity 4 inl ?1 1/2 +1 lsb voltage divide r temperature coefficient ?v w /?t code = 0x80 5 ppm/c full - scale error v wfse code = 0xff ?2 ?1 +0 lsb zero - scale error v wzse code = 0x00 0 +1 +2 lsb resistor terminals voltage range 5 v a,b,w v ss v dd v capacitance 6 ax, bx c a,b f = 1 mhz, measu red to gnd, code = 0x80 25 pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 0x80 55 pf common - mode leakage i cm v a = v b = v dd /2 1 na shutdown current 7 i shdn 0.02 5 a digital inputs input logic hig h v ih 2.4 v input logic low v il 0.8 v input logic high (sda and scl) v ih v ss = 0 v 0.7 v l v l + 0.5 v input logic low (sda and scl) v il v ss = 0 v ? 0.5 0.3 v l v input current i il v in = 0 v or +5 v 1 a input capacitance 6 c il 5 pf digital outputs sda v ol i sink = 3 ma 0.4 v v ol i sink = 6 ma 0.6 v o1, o2 v oh i source = 40 a 4 v o1, o2 v ol i si nk = 1.6 ma 0.4 v sdo v oh r l = 2.2 k? to v dd v dd ? 0.1 v sdo v ol i sink = 3 ma 0.4 v three - state leakage current i oz v in = 0 v or +5 v 1 a output capacitance 6 c oz 3 8 pf
ad5263 data sheet rev. f | page 4 of 28 parameter symbol conditions min typ 1 max unit power supplies logic supply 8 v l 2.7 5.5 v power single - supply range v dd range v ss = 0 v 4.5 16.5 v power dual - supply range v dd/ss range 4.5 7.5 v logic supply current 9 i l v l = +5 v 25 60 a positive supply current i dd v ih = +5 v or v il = 0 v 1 a negative supply current i ss v ss = C 5 v 1 a power dissipation 10 p diss v ih = +5 v or v il = 0 v, v dd = +5 v, v ss = C 5 v 0.6 mw power supply sensitivity pss ?v dd = +5 v 10% 0.002 0.01 %/% dynamic characteristics 6 , 11 bandwidth (3 db) bw r ab = 20 k?/50 k?/200 k? 300/150/35 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 20 k? 0.05 % v w settling time 12 t s v a = 10 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage e n_wb r wb = 10 k?, f = 1 khz, rs = 0 9 nv/ hz 1 typicals represent average readings at +25c and v dd = +5 v, v ss = ?5 v. 2 resistor position nonlinearity error (r - inl) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. i w = v dd /r for both v dd = +5 v and v ss = C 5 v. 3 v ab = v dd , wiper (v w ) = no connect . 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 the a, b, and w resistor terminals have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the ax terminals. all ax terminals are open - circuited in shutdown mode. 8 v l is limited to v dd or 5.5 v, whichever is less. 9 worst - case supply current consumed when all logic - input levels set at 2.4 v, standard characteristic of cmos logic. 10 p diss is calculated from i dd v dd . cmos logic level inputs result in minimum power dissipation. 11 all dynamic characteristics use v dd = +5 v, v ss = ?5 v, v l = +5 v. 12 settling time depends on value of v dd , r l , and c l .
data sheet ad5263 rev. f | page 5 of 28 timing characteristi cs20 k ?, 50 k ?, 200 k? versions v dd = + 5 v , v ss = C 5 v, v l = +5 v, v a = +v dd , v b = 0 v, C 40c < t a < +125c , unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit spi interface timing characteristics specifications apply to all parts 2 , 3 clock frequency f clk 25 mhz input clock pulse width t ch , t cl clock level high or low 20 ns data setup time t ds 10 ns data hold time t dh 10 ns cs setup time t css 15 ns cs high pulse width t csw 20 ns clk fall to cs fall hold time t csh0 0 ns clk fall to cs rise hold time t csh1 0 ns cs rise to clock rise setup t cs1 10 ns reset pulse width t rs 5 ns i 2 c interface timing characteristics specifi cations apply to all parts 2 , 3 scl clock frequency f scl 400 khz t buf bus free time b etween stop and start t 1 1.3 s t hd;sta hold time (repeated start ) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su;sta setup time for start condition t 5 0.6 s t hd; dat data hold time t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of b oth sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s 1 typicals represent average readings at +25c and v dd = +5 v, v ss = ?5 v 2 guaranteed by design and not subject to production test. 3 s ee timing diagrams for location of measured values. all input control voltages are specified with t r = t f = 2 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switching characteristics are measured using v l = 5 v.
ad5263 data sheet rev. f | page 6 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3. parameter value v dd to gnd ? 0.3 v to +16.5 v v ss to gnd ? 7.5 v to 0 v v dd to v ss +16.5 v v l to gnd ? 0.3 v to +6.5 v v a , v b , v w to gnd v ss to v dd terminal current, ax to bx, ax to wx, bx to wx pulsed 1 20 ma continuous 3 ma digital inputs and output voltage to gnd ?0.3 v to +7 v operating temperature range ? 40c to +85c maximum junction temperature (t j max ) 150c storage temperature range ? 65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 s ec thermal resistance 2 ja tssop- 24 143c/w 1 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a gi ven resistance. 2 package power dissipation: (t jmax ? t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other cond itions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad5263 rev. f | page 7 of 28 pin configuration and pin function descr iptions b1 1 a1 2 w1 3 b3 4 a3 5 b2 a2 w2 b4 a4 24 23 22 21 20 6 7 8 9 10 19 18 17 16 15 11 12 14 13 w3 v dd gnd dis v logic w4 v ss nc/o2 sdo/o1 shdn sdi/sda clk/sc l res/ad1 cs/ad0 ad5263 top view (not to scale) 03142-072 figure 2. pin configuration table 4 . pin function descriptions pin ame description 1 b1 resistor terminal b1 . 2 a1 resistor terminal a1 (addr = 00) . 3 w1 wiper terminal w1 . 4 b3 resistor ter minal b3 . 5 a3 resistor terminal a3 . 6 w3 wiper terminal w3 (addr = 10) . 7 v dd positive power supply, specified for +5 v to +15 v operation. 8 gnd ground . 9 dis digital interface select (spi/i 2 c select). spi when dis = 0, i 2 c when dis = 1 10 v logic 2.7 v to 5.5 v logic supply voltage. the logic supply voltage should always be less than or equal to v dd . in addition, logic levels must be limited to the logic supply voltage regardless of v dd . 11 sdi/sda sdi = 3 - wire serial data input. sda = 2 - wire seri al data input/output. 12 clk/scl serial clock input . 13 cs /ad0 chip select in spi mode. device address bit 0 in i 2 c mode. 14 res /ad1 reset in spi mode. device address bit 1 in i 2 c mode. 15 shdn shutdown. shorts wiper to terminal b, opens terminal a. tie to +5 v supply if not used. do not tie to v dd if v dd > 5 v. 16 sdo/o1 serial data output in spi mode . o pen - drain transistor requires pull - up resistor. digital output o1 in i 2 c mode. c an b e used to drive external logic. 17 nc/o2 no connection in spi mode. digital output o2 in i 2 c mode. c an be used to drive external logic. 18 v ss negative power supply . s pecified for operation from 0 v to C 5 v. 19 w4 wiper terminal w4 (addr = 11) . 20 a4 r esistor terminal a4 . 21 b4 resistor terminal b4 . 22 w2 wiper terminal w2 (addr = 01) . 23 a2 resistor terminal a2 . 24 b2 resistor terminal b2 .
ad5263 data sheet rev. f | page 8 of 28 typical performance characteristics r ab = 20 k? , unle ss otherwise noted. rheos ta t mode dn l (lsb) code (decimal) ?1.0 32 0 ?0.8 ?0.4 ?0.2 64 96 128 0 0.4 0.2 ?0.6 03142-073 160 192 224 256 0.8 0.6 1.0 5v +15/0v figure 3. r - dnl vs. code vs. supply voltage ?1.0 32 0 ?0.8 ?0.4 ?0.2 64 96 128 0 0.4 0.2 ?0.6 160 192 224 256 0.8 0.6 1.0 5v +15/0v 03142-002 rheostat mode inl (lsb) code (decimal) figure 4. r - inl vs. code vs. supply voltage ?1.0 32 0 ?0.8 ?0.4 ?0.2 64 96 128 0 0.4 0.2 ?0.6 03142-003 160 192 224 256 0.8 0.6 1.0 ?40c +25c +85c +125c rheostat mode dnl (lsb) code (decimal) figure 5. r - dnl vs. code; v dd = 5 v ?1.0 32 0 ?0.8 ?0.4 ?0.2 64 96 128 0 0.4 0.2 ?0.6 03142-004 160 192 224 256 0.8 0.6 1.0 rheos ta t mode in l (lsb) code (decimal) ?40c +25c +85c +125c figure 6. r - inl vs. code; v dd = 5 v ?1.0 32 0 ?0.8 ?0.4 ?0.2 64 96 128 0 0.4 0.2 ?0.6 03142-005 160 192 224 256 0.8 0.6 1.0 potentiometer mode in l (lsb) code (decimal) 5v +15/0v figure 7 . inl vs. code vs. supply voltage 03142-007 ?1.0 32 0 ?0.8 ?0.4 ?0.2 64 96 128 0 0.4 0.2 ?0.6 160 192 224 256 0.8 0.6 1.0 ?40c +25c +85c +125c potentiometer mode in l (lsb) code (decimal) figure 8 . inl vs. code vs. supply voltage
data sheet ad5263 rev. f | page 9 of 28 03142-007 ?1.0 32 0 ?0.8 ?0.4 ?0.2 64 96 128 0 0.4 0.2 ?0.6 160 192 224 256 0.8 0.6 1.0 ?40c +25c +85c +125c potentiometer mode in l (lsb) code (decimal) figure 9 . inl vs. code; v dd = 5 v ?1.0 32 0 ?0.8 ?0.4 ?0.2 64 96 128 0 0.4 0.2 ?0.6 160 192 224 256 0.8 0.6 1.0 ?40c +25c +85c +125c potentiometer mode dn l (lsb) code (decimal) 03142-008 figure 10 . dnl vs. code; v dd = 5 v 0 20 60 80 ?40 120 ?20 40 100 ?2.5 ?1.5 ?1.0 ?2.0 ?0.5 0 fse (lsb) tempera ture ( c) 03142-009 v dd /v ss = +4.5/0v v dd /v ss = 5v v dd /v ss = +16.5/0v figure 11 . full - scale error vs. temperature 2.0 0.2 0.6 1.0 1.4 1.8 0 20 60 80 ?40 120 ?20 40 100 zse (lsb) tempera ture ( c) v dd /v ss = +16.5/0v v dd /v ss = 5v v dd /v ss = +4.5/0v 0 0.8 1.2 0.4 1.6 03142-010 figure 12 . zero - scale error vs. temperature i ss @ v dd /v ss = 5v 03142-011 10 1 0.1 0.01 0.001 ?40 0 40 80 120 i dd /i ss supply current (a) temperature ( c) v logic = 5v v ih = 5v v il = 0v i dd @ v dd /v ss = 5v i dd @ v dd /v ss = +15/0v figure 13 . supply current vs. temperature 03142-012 10 1 0.1 0.01 0.001 ?40 0 40 80 120 shutdown current (a) tempera ture ( c) v dd /v ss = +15/0v v dd /v ss = 5v figure 14 . shutdown current vs. temperature
ad5263 data sheet rev. f | page 10 of 28 27 26 25 24 22 23 ?40 0 40 80 120 03142-013 i logic (a) temperature ( c) v dd /v ss = +15/0v v dd /v ss = 5v figure 15 . i logic vs. temperature r on @ v dd /v ss = +5/0v r on @ v dd /v ss = 5v r on @ v dd /v ss = +15/0v ?5 0 5 10 15 03142-014 wiper resis t ance (?) v bias (v) 45 75 50 60 70 85 80 65 55 figure 16 . wiper on - resistance vs. bias voltag e ?700 32 300 ?500 ?100 100 64 96 128 0 700 500 ?300 03142-015 160 192 224 256 rheos ta t mode tempco (ppm/ c ) code (decimal) 20k? 50k? 200k? figure 17 . rheostat m ode tempco ?r wb /?t vs. code ?250 32 0 ?200 ?100 ?50 64 96 128 0 150 50 100 ?150 160 192 224 256 potentiometer mode tempco (ppm/ c ) code (decimal) 20k? 50k? 200k? 03142-016 figure 18 . potentiometer mode tempco ?r wb /?t vs. code 1m ?60 0 100k 10k ?42 ?30 ?6 1k ?12 ?18 ?24 ?36 ?48 ?54 0x01 0x02 0x80 0x40 0x20 0x04 0x08 0x10 t a = 25 c v a = 50mv rms v dd /v ss = 5v 03142-017 gain (db) frequenc y (hz) figure 19 . gain vs. frequency vs. code; r ab = 20 k? 1m ?60 0 100k 10k ?42 ?30 ?6 1k ?12 ?18 ?24 ?36 ?48 ?54 03142-018 0x01 0x02 0x80 0x40 0x20 0x04 0x08 0x10 t a = 25 c v a = 50mv rms v dd /v ss = 5v gain (db) frequenc y (hz) figure 20 . gain vs. frequency vs . code; r ab = 50 k?
data sheet ad5263 rev. f | page 11 of 28 gain (db) ?60 0 100k 10k ?42 ?30 ?6 1k ?12 ?18 ?24 ?36 ?48 ?54 frequenc y (hz) 0x01 0x02 0x80 0x40 0x20 0x04 0x08 0x10 03142-0-019 t a = 25c v a = 50mv rms v dd /v ss = 5v figure 21 . gain vs. frequency vs. code; r ab = 200 k? 1m ?60 0 100k 10k ?42 ?30 ?6 1k ?12 ?18 ?24 ?36 ?48 ?54 03142-020 r = 50k? 150khz r = 200k? 35khz t a = 25c v dd /v ss = 5v v a = 50mv rms gain (db) frequenc y (hz) r = 20k? 300khz figure 22 . gain vs. frequency at C 3 db bandwidth 1m 0 80 10k 1k 40 20 100 60 100k 03142-021 code = 0x80, v a = v dd , v b = 0v +psrr @ v dd /v ss = 5v dc 10% p-p ac ?psrr @ v dd /v ss = 5v dc 10% p-p ac psrr (?db) frequency (hz) figure 23 . psrr vs. frequency v w code = 0x80 v dd /v ss = 5.5v v b /v a = 5v 03142-022 ch1 50.0mv m100ns a ch2 2.70v 1 figure 24 . digital feedthrough v w v dd /v ss = 5/0v v a = 5v v b = 0v 03142-023 t ch1 50.0mv m2.00s t20.00% a ch2 2.00v 1 figure 25 . midscale glitch; code 0x80 to 0x7f (4.7 nf capacitor used from wiper to ground) v w v dd /v ss = 5.5v v a /v b = 5v cs 03142-024 ch1 5.00v ch2 5.00v m400ns a ch1 2.70v 2 1 figure 26 . large signal settling time; code 0x00 to 0xff
ad5263 data sheet rev. f | page 12 of 28 5 ?0.5 0.5 10 15 20 0 1.0 0 ?1.0 03142-025 r ab = 20k? t a = 25 c a vg C 3 a vg a vg C 3 in l (lsb) |v dd ? v ss | (?v) figure 27 . inl vs. supply voltage 5 ?1.0 ?0.5 ?1.5 1.0 1.5 0.5 10 15 20 0 2.0 0 ?2.0 03142-026 r ab = 20k? t a = 25 c r-in l (lsb) |v dd ? v ss | (v) a vg C 3 a vg a vg C 3 figure 28 . r - inl vs. supply voltage
data sheet ad5263 rev. f | page 13 of 28 test circuits figure 29 to figure 39 define the test conditions used in the electrical characteristics 20 k ?, 50 k?, 200 k ? ve rsions section and the timing characteristics 20 k ?, 50 k ?, 200 k ? ve rsions . 03142-028 v ms a w b dut v+ v+ = v dd 1lsb = v+/2 n figure 29 . test circuit for potentiometer divider nonlinearity error (inl, dnl) 03142-029 no connect i w v ms a w b dut figure 30 . test circuit for resistor position nonlinearity error (rheostat operation; r - inl, r - dnl) 03142-030 v ms1 v ms2 v w a w b dut r w = [v ms1 ? v ms2 ]/i w i w = v dd /r nominal figure 31 . test circuit for wiper resistance 03142-031 v ms % dd % pss (% / %) = v+ = v dd 10% psrr (db) = 20 log ms dd v dd v a v ms a w b v+ v v v figure 32 . test circuit for power supply sensitivity (pss, ps r r) 03142-032 op279 w 5v b v out offset gnd offset bias dut v in a figure 33 . test circuit for inverting gain 03142-033 b a v in op279 w 5v v out offset gnd offset bias dut figure 34 . test circuit for noninverting gain 03142-034 +15v ?15v w a 2.5v b v out offset gnd dut ad8610 v in figure 35 . test circuit for gain vs. frequency 03142-035 w b v ss t o v dd dut i sw code = 0x00 r sw = 0.1v i sw 0.1v figure 36 . test circuit for incremental on resistance
ad5263 data sheet rev. f | page 14 of 28 03142-036 v dd v ss a w b dut gnd i cm v cm nc nc figure 37 . test circuit for c ommon - mode leakage current 03142-037 v logic i logic scl sca figure 38 . test circuit for v logic cur rent vs. digital input voltage 03142-038 v in n/c w 1 b 1 b 2 w 2 rdac 1 a 1 rdac 2 v dd v ss v out cta = 20 log [v out /v in ] a 2 figure 39 . t est circuit for analog crosstalk
data sheet ad5263 rev. f | page 15 of 28 spi- compatible digital interface (dis = 0) serial data - word forma t msb lsb addr data b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 2 9 2 7 2 0 03142-039 sdi clk cs v out 1 0 1 0 1 0 1 0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 rdac register load figure 40 . ad5263 timing diagram (v a = 5 v, v b = 0 v, v w = v out ) 03142-040 t s sdi clk cs v out 1 0 1 0 1 0 v dd 0 (dat a in) dx dx t csho t c-sw lsb t css t cl t csh1 t cs1 t ch t ds t ch figure 41 . detailed spi timing diagram (v a = 5 v, v b = 0 v, v w = v out )
ad5263 data sheet rev. f | page 16 of 28 i 2 c- compatible digital interface (dis = 1) the word format maps in this section use the following abbreviations . abbreviation description s start condition. p stop condition. a acknowledge . ad1, ad0 i 2 c device address bits. must match with the logic states at pin ad1 and pin ad0 . refer to figure 49 . a1, a0 rdac channel select. rs software reset wiper (a1, a0) to midscale position. sd shutdown active high; ties wiper (a1, a0) to terminal b, opens terminal a, rdac register contents are not disturbed. to exit shutdown, the command sd = 0 must be executed for each rdac (a1, a0). o1, o2 data to digital output pins , pin o1 and pin o2 in i 2 c mode, used to drive exte r nal logic. the logic high level is determined by v l and the logic low level is gnd. w write = 0. r read = 1. d7, d6, d5, d4, d3, d2, d1, d0 data b its. x dont c are. i 2 c write mode data - word format s 0 1 0 1 1 ad1 ad0 w a x a1 a0 rs sd o1 o2 x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte i 2 c read mode data - word format s 0 1 0 1 1 ad1 ad0 r a d7 d8 d5 d4 d3 d2 d1 d0 a p slave address byte data byte 03142-041 scl sda p s p s t 8 t 9 t 9 t 8 t 3 t 2 t 1 t 4 t 7 t 5 t 10 t 2 figure 42 . detailed i 2 c timing diagram scl start by master ack b y ad5263 stop by master sda 0 1 0 1 1 ad1 ad0 r/w x a1 rs sd o1 o2 x 1 9 1 9 d7 d6 d5 d4 d3 d2 d1 d0 ack by ad5263 19 ack by ad5263 a0 03142-042 frame 1 slave address byte frame 1 instruction byte frame 1 databyte figure 43 . writing to the rdac register 03142-043 no ack by master scl sda 0 1 0 1 1 ad1 ad0 r/w d7 d6 d5 d4 d3 d2 d1 d0 1 9 19 frame 1 frame 2 start by master ack by ad5263 slave address byte rdac register stop by master figure 44 . reading data from a previously selected rdac register in write mode
data sheet ad5263 rev. f | page 17 of 28 operation the ad5263 is a quad - channel, 256 - position, digitally controlled, variable resistor (vr) device. to program the vr settings, refer to the spi - compatible digital interface (dis = 0) section and the i2c - compatible digital interface (dis = 1) section . the part has an internal power - on preset that places the wiper at midscale during power - on, simplifying the fault condition recovery at power - up. in addition , the shutd own ( shdn ) pin of ad5263 pl aces the rdac in an almost zero - power consumption state where terminal a is open circuited and the wiper w is connected to terminal b, resulting in only leakage current consumption in the vr structure. during shutdown, the vr latch settings are maintained or new settings can be programmed. when the part is returned from shutdown, the corresponding vr setting is applied to the rdac. 03142-044 bx wx ax sd bit d7 d6 d4 d5 d2 d3 d1 d0 rdac latch and decoder r s r s r s r s figure 45 . ad5263 equivalent rdac circuit programming the vari able resistor rheostat operation the nominal resistan ce of the rdac between terminal a and terminal b is available in 20 k?, 50 k?, and 200 k?. the final two or three digits of the part number determine the nominal resistance value, for example , 20 k? = 20; 50 k? = 50; 200 k? = 200. the nominal resistance (r ab ) of the vr has 256 contact points a c cessed by the wiper terminal, plus the b terminal contact. the 8 - bit data in the rdac latch is decoded to select one of the 256 possible settings. assuming a 20 k? part is used, the wiper s first connection starts at the b terminal for data 0x00. because there i s a 60 ? wiper contact resistance, such a connection yields a min i mum of 2 60 ? resistance between the w and b terminals . the second connection is the first tap point, and corresponds to 198 ? (r wb = r ab /256 + r w = 78 ? + 2 60 ?) for d ata 0x01 . the th ird connection is th e next tap point representing 27 6 ? (r wb = 78 ? 2 + 2 60 ?) for d ata 0x02, and so on. each lsb data value increase moves the wiper up the resistor ladder until th e last tap point is reached at 20 , 04 2 ? (r ab C 1 lsb + 2 r w ). figure 45 shows a simplified diagram of the equivalent rdac circuit, where the last resistor string is not accessed; ther e fore, there is 1 lsb less of the nominal resistance at full scale in addition to the wiper resistance. the gene ral equation determining the digitally programmed output resistance between the w and b terminals is w ab wb rr d dr += 2 256 )( (1) where: d is the decimal equivalent of the binary code loaded in the 8 - bit rdac register. r ab is the end - to - end resistance. r w i s the wiper resistance contributed by the on - resistance of one internal switch. in summary, if r ab = 2 0 k? and the a terminal is open circuited, the rdac latch codes in table 5 result in the corresponding output resistance, r wb . table 5 . codes and corresponding r wb resistances d ( d ec) r wb (?) output state 255 20, 04 2 full -s cale (r ab ? 1 lsb + 2 r w ) 128 10,120 midscale 1 198 1 lsb + 2 r w 0 120 zero -s cale ( wiper contact resistance) note that in the zero - scale condition a finite wiper resistance of 120 ? is present. care should be taken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between the w wiper and terminal a also produces a digitally controlled complementary resistance, r wa . when these terminals are used, the b terminal can be open ed. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is w ab wa rr d dr + ? = 2 256 256 )( (2) for r ab = 20 k? and the b terminal is open circuited, the rdac latch codes in table 6 result in the corresponding output resistance r wa . table 6 . codes and corresponding r wa resistances d ( d ec) r wa (?) output state 255 198 full s cale 128 10,120 midscale 1 20, 04 2 1 lsb + 2 r w 0 20,12 0 zero s cale
ad5263 data sheet rev. f | page 18 of 28 the typical distribution of the end - to - end resistance r ab from channel to channel matches within 1%. device - to - device matching is process - lot dependent , and it is po ssible to have 30% variation. because the resistance element is processed in thin film technology, the change in r ab with temperature has a very low temperature coefficient of 30 ppm/c. programming the pote ntiometer divider voltage output opera tion the d igital potentiometer easily generates a voltage divider at wiper - to - b and wiper - to - a proportional to the input voltage from terminal a and terminal b. unlike the polarity from v dd to v ss , which must be positive, the voltage across a to b, w to a, and w to b can be at either polarity, if v ss is powered by a negative supply. if the effect of the wiper resistance for approximation is ignored , connecting the a terminal to 5 v and the b terminal to ground produces an output voltage from the wiper to b , starting at 0 v up to 1 lsb below 5 v. each lsb step of voltage is equal to the voltage applied across terminal a to terminal b divided by the 256 positions of the potentiometer divider. because the ad5263 can be powere d by dual supplies, the general equation defining the output voltage v w with respect to ground for any valid inp ut voltages applied to terminal a and terminal b is b a w v d v d dv 256 256 256 )( ? += (3) operation of the digital potentiometer in the divider mode resul ts in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistances r wa and r wb , and not their absolute values; therefore, the temperature drift reduces to 5 ppm/c. pi n- selectable digital i nterface the ad5263 provides the flexibility of a selectable interface. when the digital interface select (dis) pin is tied low, the spi mode is engaged. when the dis pin is tied high to the v l supply, the i 2 c mode is engaged. s pi - compatible 3 - wire serial bus (dis = 0) t he ad5263 contains a 3 - wire spi - compatible digital interface (sdi, cs , and clk). the 10 - bit seria l word must be loaded with address bits a1 and a0, followed by the data byte, msb first. the format of the word is shown in the serial data - word forma t section and bit map. the positive - edge sensitive clk input requires clean tran sitions to avoid clocking incorrect data into the serial input register. standard logic families work well. if mechanical switches are used for product evaluation, they should be debounced by a flip - flop or other suitable means. when cs is low, the clock loads data into the serial register on each positive clock edge (see figure 40). table 7. ad5263 address decode table a1 a0 latch loaded 0 0 rdac 1 0 1 rdac 2 1 0 rdac 3 1 1 rdac 4 the data setup and data hold times in the specification table determine the valid timing requirements. the ad5263 uses a 10- bit serial input data register word that is transferred to the internal rdac register when the cs line returns to logic h igh. note that only the last 10 bits that are clocked into the register are latched into the decoder. as cs goes high, it activates the address decoder and updates the corresponding channel according to table 7 . during shutdown ( shdn ), the serial data output (sdo) pin is forced to logic high in order to avoid power dissipation in the exte rnal pull - up resistor. for an equivalent sdo output circuit schematic, see figure 46. 03142-045 serial register cs sdi clk shdn res rs ck sdo d q figure 46 . detailed sdo output schematic of the ad5263 during reset ( res ), the wiper is set to midscale. note that unlike shdn , when the part is taken out of reset, the wiper remain s at midscale and does not revert to its pre - reset setting.
data sheet ad5263 rev. f | page 19 of 28 daisy- chain operation the serial data ou tput (sdo) pin contains an open - drain n- channel fet. this output requires a pull - up resistor i n order to transfer data to the sdi pin of the next package. this allows for daisy - chaining several rdacs from a single processor serial data line. the pull - up resistor termination voltage can be greater than the v dd supply voltage. it is recommended to increase the clock period when using a pull - up resistor to the sdi pin of the following device because capacitive loading at the daisy - chain node (sdo to sdi) be tween devices may induce time delay to subsequent devices. users should be aware of this potential problem to achieve data transfer successfully (see figure 47 ). if two ad5263 s are dais y- chained, a total of 20 bits of data is required. the first 10 bits, complying with the format shown in the serial data - word forma t section and bit map , go to u2 and the second 10 bits, with the same fo r mat, go to u1. cs should be kept low until all 20 bits are clocked into their respective serial registers. after this, cs is pulled high to complete the operation and load the rdac latch. d ata appears on sdo on the negativ e edge of the clock, thus making it available to the input of the daisy - chained device on the rising edge of the next clock. 03142-046 ad5263 ad5263 u2 spi u1 sdi clk sdo clk sdi sdo mosi v l r p 2.2k? cs clk cs cs figure 47 . daisy - chain configuration i 2 c- compatible 2 - wire serial bus (dis = 1) in the i 2 c- compatible mo de, the rdacs are connected to the bus as slave devices. referring to the bit maps in the i 2 c- compatible digital interface (dis = 1) section , the first byte of the ad5263 is a slave ad dress byte, consisting of a 7 - bit slave address and a r/ w bit. the five msbs are 01011 and the following two bits are determined by the state of the ad0 and ad1 pins of the device. ad0 and ad1 allow the user to place up to four of the i 2 c- compatible devices on one bus. the 2 - wire i 2 c serial bu s protocol operates as follows. 1. the master initiates a data transfer by establishing a start condition, which is when a high - to - low transition on the sda line occurs while scl is high (see figure 43 ). the following byte is the slave address byte, which consists of the 7 - bit slave address followed by an r/ w bit. this r/ w bit determines whether data will be read from or written to t he slave device. the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the select ed device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master read s from the slave device. if the r/ w bit is low, the master write s to the slave device. 2. in write m ode, the second byte is the instruction byte. the first bit (msb) of the instruction byte is a dont care. the following two bits, labeled a1 and a0, are the rdac subaddress select bits. the fourth msb (rs) is the midscale reset. a logic high on this bit m oves the wiper of the selected channel to the center tap where rwa = rwb. this feature effectively writes over the contents of the register, so that when taken out of reset mode, the rdac remain s at midscale. the fifth msb (sd) is the shutdown bit. a logic high causes the selected channel to open circuit at terminal a while shorting the wiper to terminal b. this o peration yields almost 0 ? in rheostat mode or 0 v in potentiometer mode. this sd bit serves the same function as the shdn pin except that the shdn pin reacts to active low. in addition , the sh dn pin affects all channels, as opposed to the sd bit, which affects only the channel being written to. it is important to note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previous setting is applied to the rdac. the next two bits are o2 and o1. they are extra programmable logic outputs that can be used to drive other digital loads, logic gates, led drivers, analog switches, etc. the lsb is a dont care bit (see the bit map in the i 2 c write mode data - word format section). after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses ( eight data bits followed by an ac knowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 43).
ad5263 data sheet rev. f | page 20 of 28 3. in read mode, the data byte follows immediately after the acknowledgment o f the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, where there are eight data bits followed by an acknowledge bit). similarly, the transitions on the sda line must o ccur during the low period of scl and remain stable during the high period of scl (see figure 44 ). note that the channel of interest is the one that was previously selected in write mode. in case s where users need to read the rdac values of both channels, they must program the first channel in write mode and then change to read mode to read the first channel value. after that, they must change back to write mode with the second channel selected and read the second channel value in read mode again. it is not necessary for users to issue the f rame 3 data byte in the write mode for subsequent readback operation. refer to figure 44 for the programming format. 4. after all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low - to - high transition on the sda line while scl is high. in write mode, the master pull s the sda line high during the tenth clock pulse to establish a stop condition (see figure 43 ). in read mode, the master issue s a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then bring s the sda line low before the tenth clock pulse, which goes high to establish a stop condition (see figure 44). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instructing the part only once. for example, after the rdac has a cknowledged its slave address and instruction bytes in the write mode, the rdac output update s on each successive byte. if different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed. additional programma ble logic output the ad5263 features additional programmable logic outputs, o1 and o2, which can be used to drive a digital load, analog switches , and logic gates. o1 and o2 default to logic 0. the voltage level can swing from gnd to v l . the logic states of o1 and o2 can be programmed in frame 2 under write mode (see figure 43 ). these logic ou tputs have adequate current driving capability to sink/source milliamperes of load. users can also activate o1 and o2 in three different ways without affecting the wiper settings. they may do the following: ? s tart , slave address byte, acknowledge, instructi on byte with o1 and o2 specified, acknowledge, s top . ? complete the write cycle with stop, then start , slave address byte, acknowledge, instruction byte with o1 and o2 specified, acknowledge, stop . ? do not complete the write cycle by not issuing the stop , the n start , slave address byte, acknowledge, instruction byte with o1 and o2 specified, acknowledge, stop . self - contained shutdown f unction shutdown can be activated by strobing the shdn pin or programming the sd bit in the write mode in struction byte. in addition, shutdown can even be implemented with the devices digital output , as shown in figure 48 . in this configuration, the device is shut down during power - up, but users are allowed to program the device. thu s, when o1 is programmed high, the device exit s from the shutdown mode and respond s to the new setting. this self - contained shutdown function allows absolute shutdown during power - up, which is crucial in ha z ardous environments, without adding extra compone nts. 03142-047 r pull-down scl o1 shdn sda ad5263 figure 48 . shutdown by internal logic output if the shutdown function is enabled by using the sd bit, see the i 2 c write mode data - word format section . table 8 and table 9 show the sequences that can place any channel in an undesirable shutdown state. table 8 . direct sequence command sequence rdac shutdown write rdac 1 , shdn rdac 2 rdac1 and r dac2 write rdac 2 , shdn rdac 1 rdac1 and rdac2 write rdac 3 , shdn rdac 4 rdac3 and rdac4 write rdac 4 , shdn rdac 3 rdac3 and rdac4 to overcome the issue, employ the fol lowing sequence , as an example for the first case : ? s tart , slave address byte, a cknow ledge , i nstruction byte (w rite rdac 1) , a cknowledge , d ata byte , a cknowledge , s top . ? s tart , slave address byte, acknowledge, instruction byte (w rite rdac 1 ), acknowledge, s top . ? s tart , slave address byte, acknowledge, instruction byte (shdn rdac 2 ), acknowledge, data byte, acknowledge, s top . table 9 . indirect s equence command sequence rdac shutdown write rdac 1, shdn rdac 1, shdn rdac 4 rdac1, rdac3, and rdac4 write rdac 3, shdn rdac 3, shdn rdac 2 rdac1, rdac2, and rdac3 to overcome this issue, swap the shdn order command , for example , w rite rdac 1, shdn rdac 4, and then shdn rdac 1.
data sheet ad5263 rev. f | page 21 of 28 multiple devices on one bus figure 49 shows four ad5263 devices on the same serial bus. each has a different slave address because the states of their ad0 and ad1 pins are different. this allows each rdac within each device to be written to or read from independently. the master device output bus line drivers are open - dr ain , pull - downs in a fully i 2 c- compatible interface. 03142-048 master ad5263 r p r p +5v sda scl ad0 5v 5v 5v ad1 sda scl ad5263 ad0 ad1 sda scl ad5263 ad0 ad1 sda scl ad5263 ad0 ad1 sda scl figure 49 . multiple ad5263 devices on one i 2 c bus level shift for nega tive voltage operati on the digital potentiometer is popular in laser diode driver and certain telecommunication equipment level - setting applications. these applications are sometimes operated between ground and some negative supply voltage so that the systems can be biased at round to avoid large bypass capacitors that may significantly impede the ac performance. like most digital potentiometers, the ad5263 can be configured with a negative supply (see figure 50 ). 03142-050 sda gnd v ss v dd scl level shifted level shifted ?5v ad5263 figure 50 . biased at negative voltage however, the digital inputs must also be level shifted to allow proper operation because the ground is referenced to the negative potential. as a result, figure 51 shows one impl ement tation with a couple of transistors and a few resistors. when v in is high, q1 is turned on and its emitter is clamped at one thres h old above ground. this threshold appears at the base of q2, which causes q2 to turn off. in this state, v out approaches ? 5 v. w h e n v in is low, q1 is turned off and the base of q2 is pulled low, which in turn causes q2 to turn on. in this state, v out approaches 0 v. beware that proper time shifting is also needed for successful communication with the device. 03142-051 v in v out ?5v ?5v q2 2n3906 q1 2n3906 +5v 0v ?5v 0v r3 1k? r1 10k? r2 10k? figure 51 . level shift for bipolar potential operation esd protection all digital inputs are protected with a series input resistor and parallel zener esd structures shown in figure 52 and fi gure 53. this protection applies to digital input pins sdi/sda, clk/scl, cs /ad0, res /ad1, and shdn . logic 340? v ss 03142-052 figure 52 . esd protection of digital pins 03142-053 a,b,w v ss figure 53 . esd protection of resistor terminals terminal voltage operating range the ad5263 positive v dd and negative v ss power supply defines the boundary conditions for proper 3 - terminal digital potent i ometer operation. supply signals present on the a, b, and w terminals that exceed v dd or v ss are clamped by the internal fo r ward - biased diodes shown in figure 54 . a v dd b w v ss 03142-054 figure 54 . maximum terminal voltages se t by v dd and v ss power - up sequence because the esd protection diodes limit the voltage compliance at the a, b, and w terminals (see figure 54 ), it is important to power v dd and v ss before applying any voltage to the a, b, and w ter minals ; otherwise, the diodes are forward biased such that v dd and v ss are powered unintentionally and may affect the rest of the circuit. the ideal power - up sequence is in the following order: gnd, v dd , v ss , v l , digital inputs, and v a/b/w . the relative or der of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v dd and v ss .
ad5263 data sheet rev. f | page 22 of 28 v logic power supply the ad5263 is capable of operating at high voltages beyond the internal logic l evels, which are limited to operation at 5 v. as a result, v l always needs to be tied to a separate 2.7 v to 5.5 v source to ensure proper digital signal levels. logic levels must be limited to v l , regardless of v dd . in addition, v l should always be less t han or equal to v dd . layout and power supply bypassing it is a good practice to employ compact, minimum - lead length layout design. the leads to the input should be as direct as possible with a minimum conductor length. ground paths should have low resista nce and low inductance. similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 f to 0.1 f ceramic disc or chip capacitors. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see figure 55 ). notice the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. 03142-055 gnd v ss v dd ad5263 v ss v dd c1 0.1f c2 0.1f c3 10f c4 10f + + figure 55 . power supply bypassing rdac circuit simulat ion model the internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the rdac s. configured as a potentiometer divider, the C 3 db bandwidth of the ad5263 (20 k? resistor) measures 300 khz at half scale. figure 22 provides the large signal bode plot characteristic s of the three available resistor versions: 20 k?, 50 k?, and 200 k?. a parasitic simulation model is shown in figure 56 . the following code provides a macro model net list for the 20 k? rdac. 03142-069 20k? c a w 25pf rdac a b c b c w 25pf 55pf figure 56 . rdac circuit simulation model for rdac = 20 k listing 1. macro model net list for rdac .param d=256, rdac=20e3 * .subckt dpot (a,w,b) * ca a 0 25e-12 rwa a w {(1-d/256)*rdac+60} cw w 0 55e-12 rwb w b {d/256*rdac+60} cb b 0 25e-12 * .ends dpot
data sheet ad5263 rev. f | page 23 of 28 applications information bipolar dc or ac ope ration from dual supplies the ad5263 can be operated from dual supplies, enabling control of ground referenced ac signals or bipolar operation. the ac signal, as high as v dd /v ss , can be a pplied directly across terminal a to terminal b, with the output taken from terminal w. 03142-056 gnd sclk v dd ad5263 c gnd mcsi sda scl v dd v ss +5.0v 5v p-p 2.5v p-p _ 5.0v d = 0x90 a1 w1 b1 a2 w2 b2 figure 57 . bipolar operation from dual supplies gain control compens ation a digital potentiometer is commonly used in gain con trol such as the noninverting gain amplifier shown in figure 58 . r1 47k? 25pf c1 vi b a r2 v o u1 w 200k? c2 4.7pf 03142-057 figure 58 . typical noninverting gain amplifier notice the rdac b terminal parasitic capacitance is connected to the op amp noninverting no de. it introduces a zero for the 1/ o term with +20 db/dec, whereas a typical op amp gbp has ? 20 db/dec characteristics. a large r 2 and finite c 1 can cause this zero s frequency to fall well below the crossover frequency. thus, the rate of closure becomes 40 db/dec and the system has 0 pha se margin at the crossover frequency. the output may ring or oscillate if the input is a rectangular pulse or step function. similarly, it is also likely to ring when switching between two gain values, because this is equivalent to a step change at the inp ut. depending on the op amp gbp, reducing the feedback resistor may extend the zero s frequency far enough to overcome the problem. a better approach is to include a compensation capacitor c2 to cancel the effect caused by c 1 . optimum compensation occurs when r1 c1 = r2 c2 . this is not an option, because of the variation of r2. as a result, one may use the relationship described and scale c2 as if r2 is at its maximum value. doing so may overcompensate and compromise the performance slightly when r2 is set at low values. however, it avoid s the gain peaking , ringing, or oscillation in the worst case. for critical applications, c2 should be found empirically to suit the need. in general, c2 in the range of a few pf to no more than a few tenths of pf is us ually adequate for the compensation. similarly, there are w and a terminal capacitances connected to the output (not shown); fortunately , their effect at this node is less significant and the compensation can be disregarded in most cases. programmable volt age reference for voltage divider mode operation ( figure 59 ), it is common to buffer the output of the digital potentiometer unless the load is much larger than r wb . not only does the buffer serve the purpose of impedance conversi on, but it also allows a heavier load to be driven. 03142-058 u1 vin w b a gnd v o ad8601 1 a1 5v vout 3 5v ad5263 ad1582 figure 59 . programmable voltage reference
ad5263 data sheet rev. f | page 24 of 28 8- bit bipolar dac figure 60 shows a low cost, 8 - bit, bipolar dac. it offers the same number of adj ustable steps , but not the precision as compared to conventional dacs. the linearity and temperature coefficient , especially at low values codes, are skewed by the effects of the digital potentiometer wiper resistance. the output of this circuit is ref o v d v ? ? ? ? ? ? ?= 1 256 2 (4) 03142-059 ab a1 w u1 vin gnd v o 1 vout adr425 +15v trim +5vref ?5vref a2 v i ad5263 op2177 v? v+ +15v ?15v op2177 v? v+ figure 60 . 8- bit bipolar dac bipolar programmable gain amplifier for applications requiring bipolar gain, figure 61 shows one implementation similar to the previous circuit. the digit al potentiometer u1 sets the adjustment range. the wiper voltage at w2 can therefore be programmed between v i and C kv i at a given u2 setting. configuring a2 in the noninverting mode allows linear gain and attenuation. the transfer function is ( ) ? ? ? ? ? ? ?+ ? ? ? ? ? ? += kk d2 r1 r2 v v i o 1 256 1 (5) where k is the ratio of r wb1 /r wa 1 set by u1. 03142-060 a1 ad5263 w1 v o a2 a2 b2 v ss v dd u2 ?kv i b1 a1 c1 v i r2 r1 ad5263 u1 w2 v dd v ss op2177 v? v+ op2177 v? v+ figure 61 . bipolar programmable gain amplifier similar to the previous example, in the simpler (and much more usual) case where k = 1, a single channel is used and u1 is replaced by a matched pair of resistors to apply v i and Cv i at the ends of the digital potentiometer. the relationship becomes i o v d2 r1 r2 v ? ? ? ? ? ? ? ? ? ? ? ? ? += 1 256 2 1 (6) if r2 is large, a compensation capacitor of a few pf may be needed to avoid any gain peaking. table 10 shows the result of adjusting d, with a2 configured with unity gain, gain of 2, and gain of 10. the result is a bipolar amplifier with linearly programmable gain and 256 - step resolution. table 10 . resul t of bipolar gain amplifier d r1 = , r2 = 0 r1 = r2 r2 = 9 r1 0 C1 C2 C 10 64 C 0.5 C1 C5 128 0 0 0 192 0.5 1 5 255 0.968 1.937 9.680 programmable voltage source with boosted output for applications that require high current adjustment, such as a la ser diode driver or tunable laser, a boosted voltage source can be considered. see figure 62. 03142-061 +v w signa l c c r bias ld v in a b v ou t u1 ad5263 u3 2n7002 u2 ?v i l ad8601 figure 62 . programmable booster voltage source in this circuit, the inverting input of the op amp forces the v out to be equal to the wiper voltage set by the digital pote n tiometer. the load current is then delivered by the supply via the n - channel fet , n1. n1 power handling must be adequate to dissipate power equal to (v in ? v out ) i l . this circuit can source a maximum of 100 ma with a 5 v supply. for precision applications , a voltage reference such as adr421 or adr03 can be applied at the a terminal of the digital potentiometer.
data sheet ad5263 rev. f | page 25 of 28 programmable 4 to 20 ma current source a programmable 4 C 20 ma current source can be implemented with the circuit shown in fi gure 63 . the ref191 is a unique low supply headroom and high current handling precision reference that can deliver 20 ma at +2.048 v. the load current is sim ply the voltage across terminal b to terminal w of the digital potentiometer divided by r s : n s ref l r dv i 2 = (7) 03142-062 ?2.048v to v l 0 to (2.048v + v l ) +5v 2 3 +5v u1 4 u2 ?5v v l r s ? r l ? ref191 gnd vin vout sleep ad5263 c1 1f 6 a b w i l op8510 v+ v? figure 63 . programmable 4 C 20 ma current source the circuit is simple, but beware of two things. first, dual - supply op amps are ideal because the ground potential of the ref191 can swing from ? 2.048 v at zero scale to v l at full scale of the potentiometer setting. although the circuit works with a single supply, the programmable resolution of the system is re duced. for applications that demand higher current capabilities, a few changes to the circuit in figure 63 produce an adjustable current in the range of hundreds of ma. first, the voltage refe r ence needs to be replaced with a high current, low dropout regulator, such as the adp3333 , and the op amp needs to be swapped with a high current, dual - supply model, such as the ad5263 . depending on the desired range of current, an appr o priate value for r s must be calculated. because of the high current flowing to the load, the user must pay attention to the load impedance so as not to drive the op amp past the pos i tive rail. programmable bidirec tional current source for applications that require bidirectional current control or h igher voltage compliance, a howland current pump can be a solution (see figure 64 ). if the resistors are matched, the load current is w l v r2b r1r2br2a i + = ) ( (8) 03142-063 ad5263 +5v r1 n? r2 a n? | l r2 b ? r2 n? c1 10pf c2 10pf r1 n? v l r l ? a 2 +15v +15v a w v+ op2177 op2177 v? v+ v? a1 ?5v ?15v ?15v figure 64 . programmable bidirectional current source r2b, in theory, can be made as small as needed to achieve the current needed within the a2 output current driving capability. in this circuit, op2177 can deliver 5 ma in either direction, and the vo ltage compliance approaches +15 v. it can be shown that the output impedance is ) ( )(2 r2br2a1r2rr1 r2ar1br1r z o + ? + = (9 ) this output impedance can be infinite if resistors r1 and r2 match precisely with r1 and r2a + r2b, respectively. on the other hand, it can be neg ative if the resistors are not matched. as a result, c1 in the range of 1 pf to 10 pf is needed to prevent oscillation.
ad5263 data sheet rev. f | page 26 of 28 programmable low - pass filter in analog - to - digital conversion applications, it is common to include an antialiasing filter to b and - limit the sampling signal. dual - channel digital potentiometers can be used to construct a second - order sallen - key low - pass filter (see figure 65 ). the design equations are 2 2 2 o o o i o s q s v v ++ = (1 0) c2c1r2r1 o = 1 (11 ) c2r2c1r1 q + = 11 (12 ) users can first select some convenient values for the capacitors. to achieve maximally flat bandwidth where q = 0.707, let c1 be twice the size of c2, and let r1 = r2. as a result, the user can adjust r1 and r2 to the same settings to achieve the desired bandwidth. 03142-064 v i u1 v o r1 a r w b r2 a r w b c2 c c1 c +2.5v v+ v? ?2.5v ad8601 adjusted to same setting figure 65 . sallen - key low - pass filter programmable oscilla tor in a classic wien bridge oscillator ( figure 66 ), the wien network ( r, r , c, c ) p rovides positive feedback, while r1 and r2 provide negative feedback. at the resonant frequency, f o , the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. with r = r , c = c , and r2 = r2a||(r2b + r diode ), the oscilla tion frequency is rc o 1 = , or rc f o 2 1 = (13 ) where r is equal to r wa , such that ab r d r 256 256 ? = (1 4) at resonance, setting 2 = r1 r2 (15 ) balances the bridge. in practice, r2 / r1 should be set slightl y greater than 2 to ensure that the oscillation can start. on the other hand, the alternating turn - on of the diodes d1 and d2 ensures that r2 / r1 is momentarily less than 2, thereby stabilizing the oscillation. once the frequency is set, the oscillation amp litude can be tuned by r2b because d d o vr2biv += 3 2 (1 6) v o , i d , and v d are interdependent variables. with proper selection of r2b , an equilibrium is reached such that v o converges. r2b can be in series with a discrete resistor to increase the ampli tude , but the total resistance should not be so large that it saturates the output. 03142-065 frequenc y adjustment 2.2nf c 2.2nf r? n? r n? b a a w v+ v? b b w w d1 d2 v o u 1 vp a vn ?2.5v +2.5v r1 n? r2b n? r2a n? r1 = r1 ? = r2b = ad5263 d1 = d2 = 1n4148 amplitude adjustment op 1 177 figure 66 . programmable oscillator with amplitude control
data sheet ad5263 rev. f | page 27 of 28 resistance scaling the ad5263 o ffers 20 k?, 50 k?, and 200 k? nominal resistances . users who need a lower resistance and the same number of step adjustments can place multiple devices in parallel. for example, figure 67 shows a simple scheme of using two channels in parallel. to adjust half of the resistance linearly per step, users need to program both channels to the same settings. 03142-066 w2 a1 b1 a2 b2 led v dd w1 figure 67 . reduce resistance by half with linear adjustment characteristics applicab le only to the voltage divider mode, by connecting a discrete resistor in parallel as shown in figure 68 , a proportionately lower voltage appears at terminal a. this translates into a finer degree of precision bec ause the step size at terminal w is smaller. the voltage can be found as ( ) ( ) r1r r1rr2 v d dv ab ab dd w || || 256 )( ? ? ? ? ? ? ? ? + = (1 7) 03142-067 w a b r1 r2 r1 << r ab v dd figure 68 . decreasing step size by lowering the nominal resistance figure 67 and figure 68 show applications in which the digital potentiometers change steps linearly. on the other hand, log taper adjustment is usually preferred in applications such as volume control. figure 69 shows another method of resis tance scaling which produces a pseudo log taper output. in this circuit, the smaller the value of r2 with respect to r ab , the more the output approaches log type behavior. 03142-068 v i v o a b r1 r2 figure 69 . resistor scaling with log adjustment characteri stics resistance tolerance , drift, and temperature coeffici ent mismatch considerations in rheostat mode operation, such as the gain control circuit of figure 70 , the tolerance mismatch between the digital potent - iometer and the di screte resistor can cause repeatability issues among various systems. because of the inherent matching of the silicon process, it is practical to apply the multichannel device in this type of application. as such, r1 should be replaced by one of the channe ls of the digital potentiometer. r1 should be pr o grammed to a specific value while r2 can be used for the adjustable gain. although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between r1 and r2. in addition, thi s approach also tracks the resistance drift ov er time. as a result, these non ideal parameters become less sensitive to system variations. 03142-070 u1 c1 v i r2 r1 1 v o + ? ad8601 w b a 1 replaced with another channe l of rdac figure 70 . linear gain control with tracking resistance tolerance and drift notice that the circuit in figure 71 can also be used to track the tolerance, temperature coefficient, and drift in this particular application. however, the characteristics of the transfer function c hange from a linear to a pseudo logarithmic gai n function. 03142-071 u1 v i v o v+ + ? ad8601 b w a r c1 figure 71 . nonlinear gain control with tracking resistance tolerance and drift
ad5263 data sheet rev. f | page 28 of 28 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 72 . 24 - lead thin shrink small outline package [tssop] (ru - 24) dimensions shown in millimeters ordering guide model 1 , 2 notes r ab (k?) temperature package description package option ordering quantity ad5263bru20 20 ?40c to +125c 24- lead tssop ru -24 62 ad5263bruz20 3 20 ?40c to +125c 24- lead tssop ru -24 62 ad5263bruz20 - reel7 3 20 ?40c to +125 c 24- lead tssop ru -24 1,000 ad5263bru50 50 ?40c to +125c 24- lead tssop ru -24 62 ad5263bru50 - reel7 50 ?40c to +125c 24- lead tssop ru -24 1,000 ad5263bruz50 3 50 ?40c to +125c 24- lead tssop ru -24 62 ad5263bruz50 -re el7 3 50 ?40c to +125c 24- lead tssop ru -24 1,000 ad5263bru200 200 ?40c to +125c 24 - lead tssop ru - 24 62 ad5263bruz200 3 200 ?40c to +125c 24- lead tssop ru -24 62 ad5263bruz200 - r7 3 200 ?40c to +125c 24- lead tssop ru -24 1,000 eval - ad5263ebz 4 evaluation board 1 the ad5263 contains 5,184 transistors. die size: 108 mil 198 mil = 21,384 sq. mil. 2 package branding: line 1 contains the model number, line 2 contains the end - to - end resistance, and line 3 contains the date code yyww. 3 z = rohs compliant part. 4 the evaluation board is shippe d with the 20 k? r ab resistor option; however, the board is compatible with all available resistor value options. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2003 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03142 -0- 10/12(f)

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